The present invention relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus which is capable of preferably manufacturing an integrated circuit having a lateral polycrystalline silicon device formed on an insulating film on a vertical power device and which can be manufactured by a simple manufacturing process.
Hitherto, integrated circuits have been manufactured by using single-crystalline silicon. In recent years, development in a technique for precisely forming a device has realized large scale integration. Thus, a trend of integrating various circuits and integrating a system on one chip has been made apparent. Under the circumstance above, there has been required to integrally form circuits of different types, such as high voltage devices, power devices, analog circuits and digital circuits.
In general, a structure in which a control circuit for a vertical power device is formed on the vertical power device satisfactorily improves the characteristic of the device.
FIGS. 1 and 2 are structural views of an inverter apparatus for rotating a DC motor. The apparatus has power devices each comprising an IGBT. The inverter apparatus has six IGBTs 401 to 406 forming a three-phase inverter, six diodes 411D to 416D respectively connected to the IGBTs 401 to 406 in parallel and a drive circuit IC 420 for operating the IGBTs 401 to 406. However, the foregoing inverter apparatus composed of the IGBTs 401 to 406, diodes 411D to 416D and the drive circuit 420, which are disposed individually, involves an excessively large number of elements. Thus, the cost of the apparatus cannot be reduced.
Referring to FIG. 2, a portion of the drive circuit 420 surrounded by a dashed line is an upper drive circuit 420a for operating the upper IGBTs 401 to 403. The structure of the upper drive circuit 420a will now be described. When an ON-state signal has been supplied to a high voltage MOSFET 421, which is a level shifter, constant currents flow to operate the upper CMOS drive circuit 422 comprising a CMOS inverter and the like so that the upper IGBTs 401 to 406 are operated.
As the power source for the upper drive circuit, a capacitor 424 electrically charged by a high voltage diode 423 are employed. However, if a control circuit, such as the drive circuit 420, is fabricated on a high voltage and high-current device (the IGBT), noise generated by the high-current device arises a risk that the control circuit encounters a malfunction. To prevent the malfunction, it is preferable that the control circuit and the power device be completely be isolated from each other by, for example, an oxide film.
As pn junction isolation technique is insufficient to satisfactorily electrically isolate the power device and its appendix circuit from each other, dielectric isolation or a SOI (Silicon On insulator) substrate as shown in FIG. 3 have been usually employed. Since the dielectric isolation process of the foregoing type includes a step of joining two substrates and a step of forming an embedded isolation region, a structure having a voltage resistance exceeding 600 V excessively raises the cost. However, an alternative low cost technique has not been available at present. Moreover, the cost of the single crystalline silicon for forming the substrate, as well as the cost of the dielectric isolation technique, enlarges the cost of the semiconductor device.
If the lattices are not aligned to the film allowed to grow on the single crystalline substrate, displacement takes place in the grown film and, thus, there arises a problem in that leak current are generated and the characteristic of the device deteriorates. Since the single crystalline substrate must satisfy the requirement of the lattice alignment as described above, combinations of various materials are limited. Therefore, selection of materials cannot freely be performed.
In order to reduce the cost of a transistor, which is the basic device for the semiconductor circuit, the following attempts (1) to (3) have been made such that various transistors are manufactured by using polycrystalline silicon formed on the insulating film in an amorphous state in place of the conventional and expensive single crystalline silicon. The transistor of the foregoing type has a characteristic that the polycrystalline silicon on the insulating film can easily be insulated and isolated from each other by a trench (a groove).
(1) Since a MOS transistor using the amorphous silicon can easily be formed at relatively low temperatures, it has been widely used as TFT (Thin Film Transistor) in a liquid crystalline display apparatus using a glass substrate or the like. However, the polycrystalline silicon MOS transistor has an original problem of non-uniform characteristics. PA1 (2) A technique using a polycrystalline silicon bipolar transistor has been disclosed by, for example, K. Throngnumchai ("An Intelligent Discrete Power MOSFET with Shorted Load Protection Using Thin-Film Bipolar Transistor", Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo. pp. 144 to 149). According to the thesis above, a lateral thin film bipolar transistor made of polycrystalline silicon formed by a double diffusion self-alignment technique has been reported. PA1 (3) As another device required to be manufactured by using the polycrystalline silicon, an IGBT (Insulated Gate Bipolar Transistor) for controlling electric power can be available. However, the IGBT is a device requiring storage of carriers and conductivity modulation and the polycrystalline silicon having a small life time is considered that carriers cannot easily be stored. Therefore, the IGBT cannot easily be formed. Moreover, since the polycrystalline silicon having a multiplicity of grains has a great resistance and a low mobility, the ON-state resistance is enlarged unintentionally. Therefore, the polycrystalline silicon is considered to be not suitable to manufacture the IGBT which is a high voltage and high current device. Furthermore, the polycrystalline silicon having great ON-state resistance is considered to be not suitable to manufacture another transistor except the IGBT.
The above-mentioned thesis discloses a contrivance using the lateral bipolar transistor to serve as a protective circuit. In order to apply the foregoing structure to an accurate analog circuit, a high-performance polycrystalline silicon bipolar transistor equivalent to the single crystalline bipolar transistor has been required. If a vertical polycrystalline silicon bipolar transistor is realized, combination with a polycrystalline silicon CMOS (Complementary Metal Oxide Semiconductor) circuit is expected to realize an accurate BiCMOS circuit. Thus, an intelligent power device can be manufactured with a low cost.
If a low cost and high performance MOS transistor, bipolar transistor or an IGBT can be manufactured by using the above-mentioned polycrystalline silicon, it might be considered to manufacture a CMOS transistor, a bipolar transistor or a lateral IGBT by forming a polycrystalline layer on a power device, such as the vertical MOSFET or the vertical IGBT. The above-mentioned method is able to considerably reduce the manufacturing cost as compared with the method for manufacturing a device by the dielectric isolation or the SOI. The foregoing method has an advantage that an active layer of transistors forming the appendix circuit can be formed by a polycrystalline silicon on the vertical MOSFET.
The appendix circuit of the foregoing type will now be described.
CMOS
In recent years, excellent polycrystalline silicon can be manufactured by annealing amorphous silicon or by laser-annealing polycrystalline silicon. However, if ion implantation is performed as shown in FIG. 4A after the polycrystalline silicon layer has been formed, the crystallinity of the polycrystalline silicon layer is ruptured and it is formed into amorphous state when impurities are doped to form channels. Thus, the characteristic deteriorates.
If the thickness of the active layer is large, the crystallinity can be recovered in the following thermal process by using the polycrystalline portion left in the bottom of the active layer. However, since the characteristics of the device can be improved in inverse proportion to the thickness of the active layer, the thickness is required to be reduced as much as possible.
If ions are implanted to form the channels in the amorphous silicon film before the amorphous silicon is formed into a polycrystalline state by the solid-phase growth, polycrystalline silicon exhibits excellent crystallinity.
However, the method in which the amorphous is allowed to grow to the polycrystalline silicon and which involves the n-channel and the p-channel being formed adjacently as shown in FIG. 4B encounters a problem in that the diffusion of impurities cannot be controlled in the solid-phase growth step in a case where, for example, a CMOS consisting of nMOS (n-channel MOS) and pMOS (p-channel MOS) is formed.
Hetero Junction Transistor
In a case where a thin film transistor is manufactured by using the polycrystalline silicon, there arises a problem in that the mobility of the channel is unsatisfactorily low. To overcome the foregoing problem, a method for raising the mobility may be employed in which, for example, a thin polycrystalline silicon layer is deposited on a polycrystalline silicon germanium layer followed by distorting the polycrystalline silicon layer.
An energy band of a p-channel thin film transistor is as shown in FIG. 5A. As can be understood from FIG. 5A, a two-dimensional electron gas layer is generated in the interface between the polycrystalline silicon layer and the polycrystalline silicon germanium layer, thus causing the mobility of the channel to be raised.
In a case of an n-channel, the energy band becomes as shown in FIG. 5B.
As can be understood from FIG. 5B, no 2DEG (Two Dimensional Electron Gas) layer is generated in the interface between the polycrystalline silicon layer and the polycrystalline silicon germanium layer. In this case, the mobility of the channel cannot be improved considerably.
In order to improve the mobility in the n-channel thin film transistor, the polycrystalline silicon germanium layer is distorted in place of the polycrystalline silicon layer. Although the mobility of the n-channel can be improved in this case, the mobility of the p-channel cannot be improved satisfactorily.
Therefore, three or more polycrystalline semiconductor layers are required for the CMOS to simultaneously improve the mobility of the p-channel and that of the n-channel. Thus, the manufacturing process and manufacturing system becomes too complicated.
Lateral MOSFET
FIG. 6 is a cross sectional view showing the structure of a high voltage MOSFET. The high voltage MOSFET has an n-type drift region 3 formed on an oxide film 2 formed on a polysilicon substrate 1, the n-type drift region 3 being made of polysilicon. In the n type drift region 3, an n-type drain region is selectively formed to have a depth to reach the oxide film 2. A drain electrode 5 is formed on the n-type drain region 4.
Similarly, p-type (or n.sup.-) base region 6 is selectively formed from the surface of the n-drift region 4 to the oxide film 2. An n.sup.+ source region 7 is selectively formed from the surface of the p-type base region 6 to the oxide film 2.
A source electrode 8 is formed on the n.sup.+ source region 7.
A gate insulating film (not shown) is formed on a portion of the p-type base region 6, a portion of the n-type source region 7 and a portion of the n-type drift region 3. A gate electrode 9 is formed on the gate insulating film.
Since the foregoing regions 3, 4, 6 and 7 of the foregoing high voltage MOSFET are made of polysilicon, a potential barrier exists in each grain boundaries. The barrier is, just below the gate, lowered attributable to the application of the gate voltage so that the passage of electrons through the grain boundary is permitted. However, the drift region having no gate results in the mobility of the bulk. That is, the drift region 3 must be applied with voltage when an electric current flows through the grain boundary in order to pass the barrier existing in the grain boundary. Therefore, a method of lowering the barrier of the grain boundary is an essential fact.
As a technique for lowering the barrier of the grain boundary, a method using a MOS gate to form a channel is available as described above. However, a channel cannot easily be formed by the MOS gate in the drift region because a great electric field is applied.
Thus, the high voltage polysilicon MOSFET has a problem in that voltage of a certain level must be applied between the source and the drain to cause an electric current to flow. Since a high voltage level of about 10 V is usually required, a critical problem arises when a high voltage IC is manufactured by using the polysilicon. As a result, there arises a problem in that the ON-state voltage is raised unintentionally. Lateral MOSFET.
FIG. 7 is a schematic view showing the structure of the lateral MOSFET. The MOSFET shown in FIG. 7 has a field oxide film 12 formed on a p-type high voltage silicon substrate 11. A polycrystalline silicon layer 13 serving as a p-channel MOSFET and an n-channel MOSFET is selectively formed on the field oxide film 12. In the polycrystalline silicon layer 13 of the p-channel MOSFET, there are sequentially formed a p-type source region 14, an n-type base region 15, a p-offset region 16 and a p-type drain region 17. On the p-type source region 14, there is formed a source electrode (not shown). On the n-type drain region 17, there is formed a drain electrode (not shown).
A gate electrode 19 is, on a gate oxide film 18, formed on a region from an end of the p-type source region 14 to the p-offset region 16 through the n-type base region 15.
Similarly, the polycrystalline silicon layer 13 of the n-channel MOSFET has an n-type source layer 21, a p-type base region 22, an n.sup.- offset region 23 and an n-type drain region 24 formed in parallel in this sequential order. On the n-type source layer 21, there is formed a source electrode (not shown). On the n-type drain region 24, there is formed a drain electrode (not shown).
A gate electrode 26 is, on a gate oxide film 25, formed on a region from an end of the n-type source layer 21 to the n.sup.- offset region 23 through the p-type base region 22.
Since the MOSFET of the foregoing type has an offset region, the voltage resistance can be improved. In the case of the N channel MOSFET, the n.sup.- offset region 23 has a high potential and the silicon substrate 11 has a low potential. Therefore, the n.sup.- offset region 23 is, from the oxide film 12, depleted when the gate is turned off. Therefore, even if impurities by a quantity of about 2.times.10.sup.12 cm.sup.-2 are doped into the n.sup.- offset region 23, high voltage resistance can be realized. Moreover, a required voltage resistance can be obtained by adequately determining the length of the offset region.
However, the p-channel MOSFET having the silicon substrate 11, which is a low potential, and the active layer side which is a high potential, involves the depletion layer being not expanded toward the p-offset region 16. The depletion layer expands from the n-type base region 15. If voltage resistance of, for example, 60 V is obtained in this case, the impurity density in the p-offset region 16 must be lowered. This results in high-resistance in the p-offset region 16 when the gate is turned on, thus causing a problem to arise in that the ON-state resistance is enlarged excessively. In the case of the P channel MOSFET in which the silicon substrate 11 is the low potential and the n-type base region 15 is the high potential, there arises a problem of leakage because the bottom surface of the n-type base region 15 is inverted also when the gate is turned off. Since each of the n-channel and p-channel MOSFETs has a restrained mobility of carriers as compared with a MOSFET on a single crystalline silicon, there arises a problem that the MOSFET of the foregoing type has greater ON-state resistance as compared with the MOSFET on the single crystalline silicon.
In addition to the above-mentioned structures, some lateral MOSFETs have structures as shown in FIGS. 8 to 10. FIG. 8 is a plane view showing the structure of the MOSFET of this type. FIG. 9 is a cross sectional view taken along line 9--9 shown in FIG. 8. FIG. 10 is a cross sectional view taken along line 10--10 shown in FIG. 8. The MOSFET has, as shown in FIGS. 8 to 10, an n-channel structure in which a polycrystalline silicon layer is formed on the oxide film 12.
Lateral High Voltage Diode
FIG. 11 is a cross sectional view showing a lateral and high voltage diode manufactured by using dielectric isolation. An n silicon layer (an active layer) 33 is formed on a semiconductor substrate 31 through an isolation insulating film 32. A dense n.sup.+ layer 34 is formed in the bottom portion of the active layer 33. In the active layer 33, a p-type anode layer 35 and an n-type cathode layer 36 apart from the p-type anode layer 35 are formed. Each of the p-type anode layer 35 and the n-type cathode layer 36 has an anode electrode 37 and a cathode electrode 38.
With the lateral diode having the above-mentioned structure, an inverted bias state is considered in which, for example, the anode electrode 37 and the semiconductor substrate 31 are grounded and positive voltage is applied to the cathode electrode 38. At this time, the voltage applied to the cathode electrode 38 is applied to a depletion layer formed in the active layer below the n-type cathode layer 36.
Therefore, if the thickness of the active layer portion of the n-type cathode layer 36 is large or if the active layer is too thin and thus the n-type cathode layer 36 does not reach the isolation insulating film 32, a required voltage resistance cannot be realized.
The appendix circuit has the above-mentioned structure.
However, it is considered that the thickness of the polycrystalline silicon for forming the gate is required to be 0.5 .mu.m or greater to satisfactorily lower the gate resistance of the vertical MOSFET. When a transistor is manufactured from a polycrystalline silicon, the thickness of the polycrystalline layer is required to be reduced as much as possible because the characteristic of the device can be improved in a case where the polycrystalline layer has a small thickness. Therefore, when the polycrystalline silicon gate used for the vertical MOSFET and the polycrystalline silicon transistor are integrally formed, excellent characteristics cannot be realized from the two elements. Thus, an integrated circuit in which the vertical MOSFET and the appendix circuit are integrated has not been realized yet.
Thickness
If the active layer has a large thickness, a structure, for example, V-shape groove, for isolating devices in the lateral direction must be formed. Therefore, the area of the isolating groove region is enlarged. Thus, the machining process cannot easily be performed and the effective area of the device is reduced. As a result, the cost of the integrated circuit of the high voltage device is enlarged.
If directly bonded substrates are employed to obtain a substrate comprising an active layer having a small thickness, the isolating oxide film can be thickened because it is formed by heat oxidation. Since a wafer portion, which is formed into the active layer, is formed by polishing, the thickness of the wafer cannot easily be uniformed in a case where a thin film wafer is required. Although SIMOX (Separation by Implanted Oxygen) enables a thin active layer to be obtained, the thickness of an isolating oxide film cannot be enlarged in the case where the voltage resistance is strengthened.
Note that SIMOX is a method of forming an oxide film in, for example, a silicon substrate to perform complete dielectric isolation. Specifically, oxygen ions are implanted with a density of 10.sup.18 ions/cm.sup.2 or denser into a silicon substrate so that oxygen atoms are distributed into a predetermined depth. Groups of oxygen atoms in the island configuration are allowed to grow into a layer shape in a process for restoring the crystallinity of the surface of the substrate by a predetermined heat treatment. As a result, an oxide film having a thickness of about 200 nm is formed in the substrate.
Since SIMOX has the process for allowing the groups of oxygen atoms from the island configuration into the layer shape to form the oxide film as described above, SIMOX suffers from a problem in that the thickness of the oxide film cannot be reduced to be smaller than a certain thickness. That is, although a satisfactory voltage resistance can be realized if the internal oxide film has a large thickness, the oxide film distorts the upper polycrystalline silicon layer. Thus, the polycrystalline silicon layer is formed into fine crystalline grains, thus there arises a problem of crystalline defects. As a result, the mobility of, for example, the nMOS channel is lowered to about 100 cm.sup.2 /Vs and dispersion becomes excessive as compared with the CMOS formed on a bulk.
Difference in Manufacturing Process
The vertical power devices, such as the vertical MOSFET, are mainly manufactured by a method having the steps of forming a polycrystalline silicon gate electrode; and using an end of the gate electrode as a mask to form the channel region and the source region by the double diffusion self-alignment method. It is preferable for a lateral MOS transistor using the polycrystalline silicon that predetermined impurities be introduced into the channel region before the gate electrode is formed. Therefore, when an appendix circuit comprising the polycrystalline silicon is formed on the vertical power device, manufacturing processes cannot easily be shared. Thus, there arises a problem in that the manufacturing cost cannot satisfactorily be reduced.
As described above, a low-cost semiconductor apparatus having excellent performance cannot easily be realized by using the polycrystalline semiconductor.
If the vertical power device and an appendix circuit are integrally formed, there arises a problem in that the characteristic of the power device or that of the appendix circuit deteriorates excessively.